1. Technical Field
The present invention relates to a technique of a semiconductor device, and, more particularly relates to a technique that can be effectively applied to an information processing system including a nonvolatile memory and an information processing device, and to a control method of a memory module.
2. Background Art
Conventionally, there is known a combination semiconductor memory having a flash memory (32M-bit capacity) and a static random access memory (SRAM (4M-bit capacity)) integrally sealed into an FBGA (Fine pitch Ball Grid Array) package using a stack chip. The flash memory and the SRAM have an address input terminal and a data input/output terminal in common with regard to an input/output electrode of the FBGA package. However, each of the control terminals is independent of each other (for example, see Non-patent Document 1).
There is also known a combination semiconductor memory having a flash memory (1G-bit capacity) and a dynamic random access memory (DRAM (512M-bit capacity)) integrally sealed into an FBGA (Fine pitch Ball Grid Array) package using a stack chip. With the flash memory and the dynamic random access memory, an address input terminal, a data input/output terminal, and respective control terminals thereof are independent of each other with regard to an input/output electrode of the FBGA package (for example, see Non-patent Document 2).
There is also known a combination semiconductor memory having a flash memory chip and a DRAM chip integrally sealed into a lead frame package. In this combination semiconductor memory, the flash memory and the DRAM perform input and output operations using an address input terminal, a data input/output terminal, and respective control terminals in common with regard to the input/output electrode of the package (for example, see FIGS. 1 and 15 of Patent Document 1 and Patent Document 2).
There is also known a system including a flash memory handled as a main memory, and a cache memory, a controller, and a CPU (for example, see FIG. 1 of Patent Document 3).
There is also a semiconductor memory including a flash memory, a DRAM, and a transfer control circuit (for example, see FIG. 2 of Patent Document 4 and Patent Document 5).
There is also a memory module having a plurality of identical memories connected together (for example, see Patent Document 6 and Patent Document 7).
[Non-patent Document 1] “Data Sheet of Combination Memory (Stacked CSP), Flash Memory+RAM”, Model LRS1380, [online], Dec. 10, 2001, Sharp Corporation, [Searched on Aug. 21, 2002], Internet <URL:http://www.sharp.co.jp/products/device/flash/cmlist.html>
[Non-patent Document 2] “MCP data sheet”, Model KBE00F005A-D411, [online], June 2005, Samsung Electronics Co., Ltd., [Searched on Apr. 10, 2006], <URL:1177550776718—0.aspx?family_cd=MCP0>
[Patent Document 1] Japanese Patent Application Laid-open No. H05-299616
[Patent Document 2] European Patent Application Publication No. 0566306
[Patent Document 3] Japanese Patent Application Laid-open No. H07-146820
[Patent Document 4] Japanese Patent Application Laid-open No. 2001-5723
[Patent Document 5] Japanese Patent Application Laid-open No. 2002-366429
[Patent Document 6] Japanese Patent Application Laid-open No. 2002-7308
[Patent Document 7] Japanese Patent Application Laid-open No. 2004-192616